View CBTL12131_5904864.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description CBTL12131 is an integrated displayport high-speed path switch/multiplexer that allows all-in-one computer systems to efficiently manage path switching between different display modes of operation. with the cbtl12 131, video can be routed either from one displayport source (gpu1) to an integrated displayport panel and simultaneously from a second displayport source (gpu2) to an exte rnal displayport sink; or from an external displayport source to the integrated displayport panel. the device is configured as four main port s a through d, each providing four high-speed differential lanes for displayport main link (m l) channels, one high-speed differential lane for the displayport aux channel, and one si ngle-ended lane for the hpd (hot plug detect) signal. one port (port a) provides an additional alternate lane for the aux channel, in order to allow bypassing of exter nal ac-coupling capacitors for support of the ddc channel in case an external connect ed sink is a ?++dp? type cable adapter. for the path supporting the ?external source to integrated displayport panel? mode, a programmable equalizer is provided which allo ws compensation for channel loss that the external source or internal sink are unable to adequately compensate for. the equalizer is self-biasing and is programmable to five gain -frequency curves, of which one is a flat response and four are active equalization. the equalizer output can also be set to one of two levels of pre-emphasis (including flat), and also differential swing level can be set to one of two levels. all options (eq, pre-emphasis, level) are easily programmed using board-strapping (resistor, short or open) of three unique quinary input programming pins. the CBTL12131 includes additional features t hat support use of the external displayport connector in both directions: either an extern al sink (monitor or cable adapter) or external source (notebook computer) can be connected, while CBTL12131 configures the direction and termination of the related signals accordingl y. the port facing the external displayport connector (port b) is equipped with dedicated sensing circuitry which detects and reports the status of the hpd and aux lines, to suppo rt the system controller in determining and setting the proper connection status. the aux channel of port b also has switchable integrated termination, to allo w the system controller to apply the correct dc termination in case an external displayport source is connected. moreover, it affords the system controller the means to detect the type of system (sink, source or all-in-one computer) connected at port b, and apply the proper termination required in each scenario. the CBTL12131 is powered from a single 3.3 v power supply, consumes very little current while providing low inse rtion loss and low return loss high-speed differential switch channels suitable for use in displayport v1.1a interconnect. all switch and configuration settings can be performed by board-strappi ng or driving simple cmos inputs?no software or bus configuration is required. CBTL12131 is available in a 6 mm 6mm CBTL12131 displayport multiplexe r for bidirectional video in all-in-one computer systems rev. 1 ? 25 february 2011 product data sheet
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 2 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video tfbga64 package with 0.5 mm ball pitch; owing to its high level of integration and versatility, it is eminently suitable for use in computers employing bi directional displayport video. 2. features and benefits 2.1 high-speed displayport main link multiplexing ? switch path topologies supporting: ? ?dual through? mode (two gpus to two displays simultaneously) ? ?external source? mode (external source to internal display) ? supports displayport v1.1a at 2.7 gbit/s ? high-bandwidth analog pass-gate technology ? configurable equalization in ?external source? mode path ? pre-emphasis level control for equaliz er in ?external source? mode path ? very low intra-pair di fferential skew of < 5 ps ? very low inter-pair skew of < 180 ps 2.2 ddc and aux multiplexing ? switch path topologies supporting: ? ?dual through? mode (two gpus to two displays) ? ?external source? mode (external source to internal display) ? ?ac coupling bypass? mode on port a (for external ++dp sink) ? supports displayport v1.1a aux channel ? supports ddc/i 2 c-bus multiplexing ? high-bandwidth analog pass-gate technology 2.3 hpd channel management ? active logic management of hpd signals ? bidirectional hpd i/o for external connector (port b) ? hpd input for integrated dis playport display (port d) ? two hpd outputs to both gpus, one for internal (port c) and one for external video (port a) ? 5 v tolerance on all hpd inputs ? 3.3 v lvttl logic output levels for all hpd outputs ? internal 200 k pull-down resistor on port b and port d hpd input ensures default low when no sink is connected 2.4 link state detection, c onfiguration a nd reporting ? detection of dc state of aux_p and au x_n lines of external display (port b) ? filtering of hpd inte rrupt pulse from external display (port b) ? reporting of detected/filtered port b au x and hpd states via cmos outputs (to external system controller) ? aux channel bias control inputs for port b to allow configuration as source or sink
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 3 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video ? integrated high-ohmic pull-down (4.7 m ) and switchable 100 k and 500 k resistors for port b aux bias control 2.5 equalizer ? programmable equalizer for channel loss compensation from port b to port d (external source mode) ? five levels of input equalization (including flat) ? two levels of output pre-emphasis (including flat) ? two output voltage swing levels ? three quinary input control pins allow equa lization, pre-emphasis and output voltage swing selection by simple board strapping 2.6 general ? power supply 3.3 v 10 % ? low active mode supply current of 30 ma typical (dual-through mode) ? active mode supply current of 120 ma typical (external source mode, eq = on) ? esd resilience to 4 kv hbm, 1 kv cdm ? available in tfbga64 6 mm 6 mm package 3. typical system configuration 4. ordering information fig 1. CBTL12131 in typical system configuration 002aae67 3 internal display panel (sink) dp or ++dp external display (sink) dp notebook (source) gpu2 secondary video (source) gpu1 primary video (source) dp connector displayport edp connector displayport port d port b CBTL12131 port c port a dual through mode dual through mode external source mode displayport displayport table 1. ordering information type number package name description version CBTL12131et tfbga64 plastic thin fine-pitch ball grid array package; 64 balls; body 6 6 0.8 mm sot543-1
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 4 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 5. functional diagram (1) switch is in on (conducting) position when qualifier = true. fig 2. functional diagram 002aae674 aux termination configuration hpd filter aux detection 3 hpd_b_flt aux_b_n_state aux_b_p_state hpd_b aux_term_src hpd_a vdd gnd ddc_a_1 ddc_a_0 aux_a_n aux_a_p aux_b_n aux_b_p ddc_aux_sel and path_sel# and hpd_b_flt + r aux100_p r aux100_n ml_a_[3:0]n ml_a_[3:0]p ddc_aux_sel# and path_sel# and hpd_b_flt 4 ml_b_[3:0]n ml_b_[3:0]p 4 pl5 path_sel = 0: disabled path_sel = 1: enabled path_sel hpd_d hpd_c aux_c_n aux_c_p aux_d_n aux_d_p path_sel# and hpd_b_flt path_sel# ml_c_[3:0]n ml_c_[3:0]p 4 ml_d_[3:0]n ml_d_[3:0]p path_sel# 4 CBTL12131 path_sel ddc_aux_sel tst_rext port c (faces gpu for internal video) port d (faces edp connector) port a (faces gpu for external video) port b (faces external dp connector) eq r pd_hpd 200 k eq5 aux_term_snk 4 500 k + r aux500_p 100 k 100 k r aux4m7p 4.7 m r aux4m7n 4.7 m path_sel = 0: high-z path_sel = 1: active 4 lv 5 r pd_hpd 200 k
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 5 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 6. pinning information 6.1 pinning fig 3. pin configuration for tfbga64 002aae67 5 CBTL12131et transparent top view k j h g f e c b a d 2468910 1357 ball a1 index area fig 4. ball mapping for tfbga64 ml_a_0p ml_a_1p ml_a_2p ml_a_3p aux_a_p ddc_a_0 gnd hpd_b j lv 5 hpd_c aux_b_p aux_b_n h eq5 ml_c_3n pl5 g ml_c_3p ddc_ aux_sel ml_c_2n f ml_c_2p ml_b_3p ml_b_3n ml_c_1n e ml_c_1p ml_b_2p ml_b_2n ml_c_0n d ml_c_0p ml_b_1p ml_b_1n aux_c_n c aux_c_p ml_b_0p ml_b_0n aux_d_p ml_d_0p ml_d_1p ml_d_2p ml_d_3p gnd b gnd aux_b_ n_state hpd_b_ flt vdd vdd a path_ sel aux_d_n ml_d_0n ml_d_1n ml_d_2n ml_d_3n hpd_d aux_b_ p_state 002aae676 12345678910 transparent top view port d (faces edp connector) port a (faces gpu for external video) port b (faces external dp connector) port c (faces gpu for internal video) vdd aux_ term_ src ml_a_0n ml_a_1n ml_a_2n ml_a_3n aux_a_n ddc_a_1 hpd_a vdd k tst_ rext aux_ term_ snk
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 6 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 6.2 pin description table 2. pin description symbol pin type description control inputs path_sel e1 3.3 v low-voltage cmos single-ended input input to set the path configurat ion of the CBTL12131. when low, ports a and b are mutually connec ted, as well as ports c and d. when high, port b is connected to port d. ddc_aux_sel d10 3.3 v low-voltage cmos single-ended input input to select between ddc and aux terminals for port a. when high, the ddc_a_p and ddc_a_n terminals are connected to their respective aux_b_p and aux_ b_n terminals on port b. when low, the aux_a_p and aux_a_n terminals are connected to their respective aux_b_p and au x_b_n terminals on port b. eq5 e10 3.3 v low-voltage cmos quinary input equalizer setting input pin. this pin can be board-strapped to one of five decode values: short to gnd, resistor to gnd, open-circuit, resistor to vdd, short to vdd. see ta b l e 7 for truth table. pl5 d9 3.3 v low-voltage cmos quinary input pre-emphasis level setting input pi n. this pin can be board-strapped to one of five decode values: short to gnd, resistor to gnd, open-circuit, resistor to vdd, short to vdd. see table 8 for truth table. lv5 f9 3.3 v low-voltage cmos quinary input output differential swing setting input pin. this pin can be board-strapped to one of five decod e values: short to gnd, resistor to gnd, open-circuit, resistor to vdd, short to vdd. see table 9 for truth table. tst_rext f1 3.3 v low-voltage cmos single-ended input with current sensing analog input test pin for nxp use, combined with external current sensing function. should be tied to ground via an external resistor of value 10 k ? 1 %. this pin must not be left open-circuit to avoid possible erroneous engagement of test mode in normal operation. aux_term_src g1 3.3 v low-voltage cmos single-ended input input to enable source-type termination on the port b aux pair. when high, 100 k termination resistors are applied to the port b aux pair. when low, the termination resistors will be disabled (high-impedance). aux_term_snk g2 3.3 v low-voltage cmos single-ended input input to enable sink-style termination on the port b aux pair. when high, a 500 k termination resistor to vdd is applied to aux_b_p. when low, the termination resistor will be disabled (high-impedance). status outputs hpd_b_flt f10 3.3 v low-voltage cmos single-ended output this outputs a filtered version of hpd_b. aux_b_p_state d1 3.3 v low-voltage cmos single-ended output dc state (high or low) of aux_b_p signal. aux_b_n_state d2 3.3 v low-voltage cmos single-ended output dc state (high or low) of aux_b_n signal.
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 7 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video port a terminals ml_a_0p k7 differential port terminal four high-speed diff erential pairs for displayport main link signals, port a. designated as port facing the gpu for external video. port a will be exclusively connected to port b when path_sel = low, and will be high-impedance when path_sel = high. ml_a_0n j7 differential port terminal ml_a_1p k8 differential port terminal ml_a_1n j8 differential port terminal ml_a_2p k9 differential port terminal ml_a_2n j9 differential port terminal ml_a_3p k10 differential port terminal ml_a_3n j10 differential port terminal aux_a_p h10 differential port terminal high-speed differ ential pair for displayport aux signals, port a. these terminals are active when ddc_aux_sel = low only; when ddc_aux_sel = high, these are high-impedance. aux_a_n h9 differential port terminal ddc_a_0 g10 differential port terminal port a terminal intended for aux ac coupling capacitor bypass. these terminals are active when ddc_aux_sel = high only; when ddc_aux_sel = low, these are high-impedance. ddc_a_1 g9 differential port terminal hpd_a k6 3.3 v lvttl single-ended output 3.3 v lvttl hpd output for port a. when path_sel = low, this output follows the state of hpd_b (from external dp or ++dp sink). when path_sel = high, this output is always low. port b terminals ml_b_0p a7 differential port terminal four high-speed diff erential pairs for displayport main link signals, port b. designated as port facing the external dp connector. port b will be exclusively connected to port a when path_sel = low and hpd_b_flt = high, and will be exclusively connected to port d when path_sel = high. when path_sel = high, the signal ordering and association to port d ml signals is automatically corrected by internal routing, to map to the dp connector's inverted signal ordering for a dp sink-side connector. ml_b_0n b7 differential port terminal ml_b_1p a8 differential port terminal ml_b_1n b8 differential port terminal ml_b_2p a9 differential port terminal ml_b_2n b9 differential port terminal ml_b_3p a10 differential port terminal ml_b_3n b10 differential port terminal aux_b_p c10 differential port terminal high-speed differ ential pair for displayport aux signals, port b. aux_b_n c9 differential port terminal hpd_b a6 3.3 v bidirectional lvttl i/o with high-z state hpd input with 5 v tolerance or output for port b, to be connected to the external dp connector. when path_sel = low, hpd_b is configured as input (from external dp or ++dp sink). when path_sel = high, hpd_b is configured as output and follows the state of hpd_d (from internal sink), to be connected via dp connector to an external dp source. table 2. pin description ?continued symbol pin type description
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 8 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video port c terminals ml_c_0p k1 differential port terminal four high-speed di fferential pairs for displayport main link signals, port c. designated as port facing t he gpu for internal video. port c will be exclusively connected to port d when path_sel = low, and will be high-impedance when path_sel = high. ml_c_0n j1 differential port terminal ml_c_1p k2 differential port terminal ml_c_1n j2 differential port terminal ml_c_2p k3 differential port terminal ml_c_2n j3 differential port terminal ml_c_3p k4 differential port terminal ml_c_3n j4 differential port terminal aux_c_p h1 differential port terminal high-speed differ ential pair for displayport aux signals, port c. aux_c_n h2 differential port terminal hpd_c k5 3.3 v lvttl single-ended output 3.3 v lvttl hpd output for port c. when path_sel = low, this output follows the state of hpd_d (from internal sink). when path_sel = high, this output is always low. port d terminals ml_d_0p a1 differential port terminal four high-speed di fferential pairs for displayport main link signals, port d. designated as port facing the internal edp display module connector. port d will be exclusively connected to port c when path_sel = low, and will be exclusively connected to port b when path_sel = high. ml_d_0n b1 differential port terminal ml_d_1p a2 differential port terminal ml_d_1n b2 differential port terminal ml_d_2p a3 differential port terminal ml_d_2n b3 differential port terminal ml_d_3p a4 differential port terminal ml_d_3n b4 differential port terminal aux_d_p c1 differential port terminal high-speed differ ential pair for displayport aux signals, port d. aux_d_n c2 differential port terminal hpd_d a5 3.3 v lvttl single-ended input 5 v tolerant hpd input for port d, to be connected to the internal sink. supply and ground vdd b5, e2, e9, j5 power supply 3.3 v power supply pins. gnd b6, f2, j6 ground ground pins. table 2. pin description ?continued symbol pin type description
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 9 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 7. functional description 7.1 general the CBTL12131 is a high-bandwidth displayport channel switching device designed for use in all-in-one computers. it contains high-bandwidth switches arranged between four ports (a through d) to allow two different channel topologies, where each channel comprises a main link (ml), aux and hpd pa th for comprehensive displayport channel switching. one can select between two basic configurations: either ports a and c are connected to ports b and d respectively, or po rt b is connected to port d while ports a and c are high-impedance. in addition, the CBTL12131 includes circuitry to assist in detection and configuration of port b desi gnated as the port fa cing the external displayport connector. this section describes these functional blocks in detail. 7.2 main link displaypor t switches/multiplexers the main link path topology provides for four differential pairs in each port, and an equalizer for each differential pair in the path from port b to port d, as shown in figure 5 . the main link switches are operated by cmos input path_sel and further qualified by the state of internally derived signal hpd_b_flt (see section 7.6 for details). when path_sel is low, ports c and d are mutually connected, ports a and b are mutually connected only when hpd_b_flt is high, and the equalizer is turned off (isolating). when path_sel is high, ports a and c are disconnected (high-impedance) and port d is connected to port b via the equalizer. the equalizer can by bypassed or configured by quinary input eq5 to any of five equalizer se ttings (including a flat response) depending on specific application condit ions. for details on the equalizer function, please refer to section 7.7 . fig 5. main link channel topology 002aae67 7 pl5 eq output disabled/no load when path_sel = 0 path_sel = 0: pass path_sel = 1: off eq ml port a ml port b ml port c ml port d path_sel = 0 and hpd_b_flt = 1: pass else: off eq5 lv 5 table 3. main link channel configuration legend: high-z = isolating, high-im pedance; act = active, low-impedance. inputs channels comment path_sel hpd_b_flt port c - port d port a - port b port b - port d 0 0 act high-z high-z normal mode; internal display only 0 1 act act high-z normal mode with dual display 1 0 high-z high-z act external source mode with internal display not yet asserting hpd 1 1 high-z high-z act external source mode with internal display asserting hpd
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 10 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video [1] remark: signal ordering between port b and port d is inverted in order to ac hieve proper signal-to-pin mapping in accordance with sink si de status of connector at port b. table 4. main link signal mappings legend: high-z = isolating, high-impedance; act = acti ve, low-impedance; eq = ac tive, equalized/re-driven. inputs channels comment (all other ports shall be mutually isolated) path_sel hpd_b_flt port c - port d port a - port b port b - port d [1] 00 ml_c_0p act ml_d_0p ml_a_0p high-z ml_b_0p ml_b_0p high-z ml_d_3n normal mode; internal display only ml_c_0n act ml_d_0n ml_a_0n high-z ml_b_0n ml_b_0n high-z ml_d_3p ml_c_1p act ml_d_1p ml_a_1p high-z ml_b_1p ml_b_1p high-z ml_d_2n ml_c_1n act ml_d_1n ml_a_1n high-z ml_b_1n ml_b_1n high-z ml_d_2p ml_c_2p act ml_d_2p ml_a_2p high-z ml_b_2p ml_b_2p high-z ml_d_1n ml_c_2n act ml_d_2n ml_a_2n high-z ml_b_2n ml_b_2n high-z ml_d_1p ml_c_3p act ml_d_3p ml_a_3p high-z ml_b_3p ml_b_3p high-z ml_d_0n ml_c_3n act ml_d_3n ml_a_3n high-z ml_b_3n ml_b_3n high-z ml_d_0p 01 ml_c_0p act ml_d_0p ml_a_0p act ml_b_0p ml_b_0p high-z ml_d_3n normal mode with dual display ml_c_0n act ml_d_0n ml_a_0n act ml_b_0n ml_b_0n high-z ml_d_3p ml_c_1p act ml_d_1p ml_a_1p act ml_b_1p ml_b_1p high-z ml_d_2n ml_c_1n act ml_d_1n ml_a_1n act ml_b_1n ml_b_1n high-z ml_d_2p ml_c_2p act ml_d_2p ml_a_2p act ml_b_2p ml_b_2p high-z ml_d_1n ml_c_2n act ml_d_2n ml_a_2n act ml_b_2n ml_b_2n high-z ml_d_1p ml_c_3p act ml_d_3p ml_a_3p act ml_b_3p ml_b_3p high-z ml_d_0n ml_c_3n act ml_d_3n ml_a_3n act ml_b_3n ml_b_3n high-z ml_d_0p 1x ml_c_0p high-z ml_d_0p ml_a_0p high-z ml_b_0p ml_b_0p eq ml_d_3n external source mode ml_c_0n high-z ml_d_0n ml_a_0n high-z ml_b_0n ml_b_0n eq ml_d_3p ml_c_1p high-z ml_d_1p ml_a_1p high-z ml_b_1p ml_b_1p eq ml_d_2n ml_c_1n high-z ml_d_1n ml_a_1n high-z ml_b_1n ml_b_1n eq ml_d_2p ml_c_2p high-z ml_d_2p ml_a_2p high-z ml_b_2p ml_b_2p eq ml_d_1n ml_c_2n high-z ml_d_2n ml_a_2n high-z ml_b_2n ml_b_2n eq ml_d_1p ml_c_3p high-z ml_d_3p ml_a_3p high-z ml_b_3p ml_b_3p eq ml_d_0n ml_c_3n high-z ml_d_3n ml_a_3n high-z ml_b_3n ml_b_3n eq ml_d_0p
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 11 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 7.3 aux and ddc sw itches/multiplexers for all ports except port a, only a single pair of signal lines is provided. the path configuration for the aux/ddc channels follows that of the main link: when path_sel = low, ports c and d are connected; when path_sel = low and hpd_b_flt = high, also ports a and b are connected; when path_sel = high, port d is connected to port b, and ports a and c are isolated (see figure 6 ). port a additionally provides a second pair of signal lines, to allow bypassing of external ac-coupling capacitors (normally placed in se ries with the aux channel) in the case when an external ++dp cable adapter is detect ed, and therefore a dc path needs to be provided from the external dp connector?s aux_p and aux_n lines, in order to support ddc communication across those lines betw een the external graphics gpu (facing port a) and the external ++dp cable adapter. selection between the ddc and aux channels of port a is determined by the input ddc_aux_sel: when ddc_aux_sel = low, the active channel is aux_a; when ddc_aux_sel = high, the active channel is ddc_a. typically, ddc_au x_sel is driven by a qualified version of the dp ?cable detect? signal (pin 4 of a minidp connector or pin 13 of a normal dp connector) and will be high when such a cable adaptor is connected and powered. fig 6. aux and ddc channel topology 002aae67 8 path_sel = 0: off path_sel = 1: pass aux_a aux_b aux_c aux_d select between aux and ddc ddc_a hpd_b_flt = 1 and path_sel = 0 and ddc_aux_sel = 0: pass else: off hpd_b_flt = 1 and path_sel = 0 and ddc_aux_sel = 1: pass else: off path_sel = 0: pass path_sel = 1: off
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 12 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 7.4 hpd signal path the hpd signal path, unlike the main link and aux/ddc paths, uses active lvttl logic rather than passive switching. as shown in figure 7 , the topology follows that of the main link and aux channels but with the signal direction in reverse direction (since the hpd signal direction is always from sink to source). when path_sel is low, output hpd_c follows and re-drives input hpd_d and similarly hpd_a follows the logic state of input hpd_b. an integrated 200 k resistor (rpd_hpd) between hpd_b and gnd ensures a logic low when no device is conne cted to port b. when path_sel is high, hpd_b becomes an output and follows the lo gic state of hpd_d. please also refer to section 7.6 for specific details on th e hpd filtering function. table 5. aux/ddc chan nel configuration legend: high-z = isolating, high-im pedance; act = active, low-impedance. inputs channel comment (all other ports shall be mutually isolated) path_sel hpd_b_flt ddc_aux_sel port c - port d port a - port b port b - port d aux_a ddc_a 0 0 x act high-z high-z high-z normal mode; internal display only 0 1 0 act act high-z high-z normal mode with dual display 0 1 1 act high-z act high-z normal mode with dual display using ++dp display adaptor 1 0 x high-z high-z high-z act external source mode with internal display not yet asserting hpd 1 1 x high-z high-z high-z act external source mode with internal display asserting hpd fig 7. hpd channel topology 002aaf99 9 hpd_b hpd_a hpd_d hpd_c path_sel = 0: high-z path_sel = 1: active path_sel = 0: active path_sel = 1: low r pd_hpd r pd_hpd
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 13 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video [1] steady-state is shown only. a high-to-lo w transition will be fi ltered (~4 ms delay). 7.5 aux logic state detection CBTL12131 includes a helpful function to determine the dc state of the aux_b_p and aux_b_n pins thereby aiding in the detection of devices connected to the external dp connector. the dc state of these pins is output on pins aux_b_p_state and aux_b_n_state respectively, after the 1 mbit/s (typ) manc hester-encoded bitstream is removed by filtering. 7.6 hpd logic state detection to further aid in detection of externally co nnected devices on port b, the hpd_b_flt pin outputs a filtered version of pin hpd_b. th e filtering function suppresses the 1 ms (typ) low interrupt pulse from a displayport sink, thereby avoiding a false disconnect detection. only a low pulse greater than 4 ms will result in a low output on hpd_b_flt. 7.7 equalizer the equalizer function equalizes the signal on the main link channel of port b and re-drives them to port d and ultimately to the internal display panel. the equalizer is only active when path_se l is high. when path_sel is low, the equalizer is effectively disabled and present s minimum parasitic load to the main link channels. the equalizer has configurable equalization (eq) settings for its input (port b side), which can be set to one of five options by quinary input pin eq5. see ta b l e 7 for programming options. table 6. hpd channel configuration inputs outputs comment path_sel hpd_b hpd_d hpd_a hpd_b hpd_b_flt [1] hpd_c 0 0 0 0 high-z 0 0 normal mode; internal display not (yet) asserting hpd 0 0 1 0 high-z 0 1 normal mode; internal display asserting hpd 0 1 0 1 high-z 1 0 normal mode but unexpected condition; internal display not asserting hpd during normal operation 0 1 1 1 high-z 1 1 normal mode; with external sink asserting hpd 1 n/a 0 0 0 0 0 external source mode with internal display not (yet) asserting hpd 1 n/a 1 0 1 1 0 external source mode with internal display asserting hpd
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 14 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video the equalizer also has two different levels of pre-emphasis for its output (port d side), which can be set by quinary input pin pl5; as we ll as two different output differential swing levels, which can be set by quinary input pin lv5. see ta b l e 8 and ta b l e 9 for programming options. [1] only available with 400 mv output voltage swing setting (see table 9 ). table 7. equalizer settings inputs quinary notation equalizer mode (see figure 8 ) eq5 short to gnd 0 5 0db 10 k resistor to gnd 1 5 2db open-circuit 2 5 3.5 db 10 k resistor to vdd 3 5 6.5 db short to vdd 4 5 9db fig 8. equalizer gain versus frequency table 8. pre-emphasis settings inputs quinary notation output mode pl5 short to gnd 0 5 0db 10 k resistor to gnd 1 5 3.5 db [1] open-circuit 2 5 reserved 10 k resistor to vdd 3 5 reserved short to vdd 4 5 reserved 002aae977 f (mhz) 1 10 4 10 3 10 10 2 0 4 ? 4 8 12 gain (db) ? 8 eq9.0 eq6.5 eq3.5 eq2.0 eq0.0
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 15 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video [1] 600 mv level setting ove rrides pre-emphasis settings. table 9. output voltage swing settings inputs quinary notation output mode lv5 short to gnd 0 5 400 mv 10 k resistor to gnd 1 5 600 mv [1] ] open-circuit 2 5 reserved 10 k resistor to vdd 3 5 reserved short to vdd 4 5 reserved
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 16 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 7.8 aux channel bias and termination the aux lines of port b can be biased and te rminated in accordance with the displayport interoperability guid elines in accordance with the configuration for ei ther a sink or source, depending on which is required. the control input for the termination and bias are cmos inputs aux_term_src and aux_term_snk. together with the state of path_sel and hpd_b_flt (the filtered, steady state of hpd_b), these signals allow a detection scheme by which the system controller can resolve different connection scenarios of th e external displayport connector at port b: ? nothing is connected ? an external source is connected ? an external sink is connected (either with or without source detection being performed by the sink) ? an external, second all-in-o ne system (using a topology similar or equivalent to CBTL12131) at first connection time, the latter scenario ma y appear identical to the first. in this case, aux_term_snk (which applies a 500 k pull-up on aux_b_p line provided) can be toggled high in order to allo w the other system to detect a connected sink, and configure itself accordingly as a source. using aux_term_src, the system controller is able to check whether the attached device is a sink which is not asserting hpd (as some sinks will employ source detection for power saving reasons). by applying the integrated 100 k pull-up and pull-down resistors, the attached sink will detect a source and asse rt its hdp when it is ready. when hpd_b_flt is high, this means the attached device is asserting hpd and CBTL12131 will activate its source type 100 k termination resistors. when path_sel is high, this means the intern al displayport sink (embedded panel) is active, and its 1 m termination resistors will apply the correct aux bias to represent a sink device. in the default condition (path_sel, hpd_b_flt and aux_term_snk/src are all low), 4.7 m pull-down resistors are applied to the aux_b pair, in order to avoid floating conditions in case two similar systems are connected together. when both aux_term_src and aux_term_snk are high, all integrated termination resistors will be de-activat ed. for correct system operation, the system controller needs to guarantee that aux_term_src and aux_te rm_snk are never high at the same time, unless the external termination resistors are implemented.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 17 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video [1] hpd_b_flt is an internally derived signal, not an i nput to CBTL12131. hpd_b_flt will follow input hpd_b. [2] system controller will assert aux_term_snk high when user action prompts a ?toggle?, hence sy stem should configure itself as a sink. [3] system controller will assert aux_term _src high when it has determined that a sink is connected, hence system should configu re itself as a source. [4] system controller should guarantee that (aux_term_snk & aux_te rm_src) is never true for normal operation unless the external termination resistors are used. [5] aux_term_src and aux_term_snk = true are used as a disabl e mechanism for the integrated aux bias netwo rk when external termination resistors ar e used. table 10. aux channel bias and termination legend: high-z = isolating, high-impe dance; act = active, nominal-impedance. inputs aux terminations comments path_sel hpd_b_flt [1] aux_term _src aux_term _snk raux100p raux100n raux500p raux4m7p raux4m7n 0 0 0 0 high-z high-z high-z act act nothing connected. 0 0 0 1 high-z high-z act high-z act override in scenario of two systems both using CBTL12131 connected together. [2] 0 0 1 0 act act high-z high-z high-z allow sink to perform source detection. [3] 0 0 1 1 high-z high-z high-z high-z high-z [4] [5] 0 1 0 0 act act high-z high-z high-z dual display mode - normal condition. 0 1 0 1 act act high-z high-z high-z not an expected condition. already in dual display mode with source termination active. 0 1 1 0 act act high-z high-z high-z not an expected condition. already in dual display mode with source termination active. 0 1 1 1 high-z high-z high-z high-z high-z [4][5] 1 x x x high-z high-z high-z high-z high-z internal display expected to exhibit 1 m pull-up and pull-down, hence no termination needed.
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 18 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 7.9 tst_rext function pin tst_rext has a dual function. in normal o peration, this pin should be tied to analog gnd externally via a 10 k , 1 % accuracy resistor. the external resistor functions as a reference to establish accurate internal cu rrent sources for the eq output stage. the second function of this pin is to put CBTL12131 in test mode by driving it high. this test mode is for internal use only and has no use in normal operation. 8. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing. human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged-device model: ansi/eos/esd-s5.3-1- 1999, standard for esd sensitivity testing, charged-device model - component level; electr ostatic discharge association, rome, ny, usa. 9. recommended operating conditions table 11. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v t case case temperature for operation within specification ? 40 +85 c v esd electrostatic discharge voltage hbm [1] - 4000 v cdm [2] - 1000 v table 12. operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage - - 3.6 v hpd inputs - - 5.5 v t amb ambient temperature operating in free air ? 40 - +85 c
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 19 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 10. characteristics 10.1 general characteristics 10.2 displayport channel characteristics table 13. general characteristics symbol parameter conditions min typ max unit i dd supply current path_sel = 0 - 30 40 ma path_sel = 1 - 120 150 ma t startup start-up time supply voltage valid to channel specified operating characteristics --10 s t rcfg reconfiguration time path_sel state change to channel specified operating characteristics --10 s table 14. displayport channel characteristics symbol parameter conditions min typ max unit v i input voltage ? 0.3 - +2.6 v v ic common-mode input voltage 0 - 2.0 v v id differential input voltage - - +1.2 v ddil differential insertion loss channel is on; 0 hz f 1.0 ghz ? 2.0 ? 1.5 - db channel is on; f = 2.5 ghz ? 3.5--db channel is off; 0 hz f 3.0 ghz - - ? 30 db ddrl differential return loss channel is on; 0 hz f 1.0 ghz - - ? 10 db ddnext differential near-end crosstalk adjacent channels are on; 0hz f 1.0 ghz -- ? 30 db b bandwidth ? 3.0 db intercept - 2.6 - ghz t pd propagation delay from left-side port to right-side port or vice versa; path_sel = 0 --180ps from port b to port d; path_sel = 1 --2ms t sk(dif) differential skew time intra-pair - - 5 ps t sk skew time inter-pair - - 180 ps v tx_diffp-p differential peak-to-peak output voltage port d output; path_sel = 1 lv5 short to gnd - 400 - mv lv5 10 k resistor to gnd - 600 - mv v tx_preemp_ratio pre-emphasis ratio port d output; path_sel = 1 pl5 short to gnd - 0 - db pl5 10 k resistor to gnd - 3.5 - db
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 20 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 10.3 aux and ddc ports [1] time from ddc/aux input changing state to aux output changing state. includes ddc/aux rise/fall time. 10.4 hpd input, hpd output [1] low-speed input changes state on cable plug/unplug. [2] time from hpd_sink changing state to hpd changing state. includes hpd rise/fall time. 10.5 control inputs 10.6 status outputs table 15. aux and ddc po rt characteristics symbol parameter conditions min typ max unit v i input voltage ddc ? 0.3 - +3.6 v aux; single-ended; figure 9 0.16 - 0.7 v aux aux attenuation with 100 termination - 2 3.5 db v bias(dc) bias voltage (dc) aux_p; figure 9 0- 2.0v aux_n; figure 9 1.5 - 3.6 v t pd propagation delay between connected ports [1] -180- ps fig 9. aux_p and aux_n input voltage waveform 002aaf47 5 aux_p, aux_n v i gnd (0 v) v bias(dc) table 16. hpd input and output characteristics symbol parameter conditions min typ max unit v i input voltage [1] ? 0.3 - 3.6 v t pd propagation delay between connected ports [2] - 4060ns table 17. control input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage cmos inputs 2.0 - 3.6 v v il low-level input voltage cmos inputs 0 - 0.8 v i li input leakage current measured with input at v ih(max) and v il(min) --10 a table 18. status output characteristics symbol parameter conditions min typ max unit v oh high-level output voltage cmos outputs 2.5 - - v v ol low-level output voltage cmos outputs 0 - 0.2 v t t transition time 10 % to 90 % 1 - 60 ns
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 21 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 11. package outline fig 10. package outline sot543-1 (tfbga64) ball a1 index area 0.5 a 1 b a 2 unit d y e references outline version european projection issue date 00-11-22 02-04-09 iec jedec jeita mm 1.1 0.25 0.15 0.85 0.75 6.1 5.9 y 1 6.1 5.9 0.35 0.25 0.08 dimensions (mm are the original dimensions) sot543-1 mo-195 - - - - - - e 0.15 0.1 e 1 4.5 e 2 4.5 v 0.05 w 0 2.5 5 mm scale sot543- 1 t fbga64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm a max. a a 2 a 1 detail x x d e a b c d e f h j k g 2468910 1357 b a ball a1 index area y y 1 c e e e 1 b c e 2 1/2 e 1/2 e a c c b ? v m ? w m
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 22 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 23 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 12.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 11 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 9 and 20 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 11 . table 19. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 20. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 24 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 13. abbreviations msl: moisture sensitivity level fig 11. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 21. abbreviations acronym description cdm charged-device model cmos complementary metal-oxide semiconductor ddc data display channel dp displayport edp embedded displayport esd electrostatic discharge gpu graphics processor unit hbm human body model hpd hot plug detect i 2 c-bus inter-integrated circuit bus i/o input/output lvttl low voltage transistor-transistor logic ml main link
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 25 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 14. revision history table 22. revision history document id release date data sheet status change notice supersedes CBTL12131 v.1 20110225 product data sheet - -
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 26 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
CBTL12131 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 25 february 2011 27 of 28 nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors CBTL12131 displayport multiplexer for bidirectional video ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 25 february 2011 document identifier: CBTL12131 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 high-speed displayport main link multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 ddc and aux multiplexing. . . . . . . . . . . . . . . . 2 2.3 hpd channel management . . . . . . . . . . . . . . . 2 2.4 link state detecti on, configuration and reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.6 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 typical system configuration . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 main link displayport switches/multiplexers . . 9 7.3 aux and ddc switches/multiplexers . . . . . . . 11 7.4 hpd signal path . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 aux logic state detection . . . . . . . . . . . . . . . . 13 7.6 hpd logic state detection . . . . . . . . . . . . . . . . 13 7.7 equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 aux channel bias and termination . . . . . . . . . 16 7.9 tst_rext function . . . . . . . . . . . . . . . . . . . . 18 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 9 recommended operating conditions. . . . . . . 18 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 general characteristics . . . . . . . . . . . . . . . . . . 19 10.2 displayport channel characteristics . . . . . . . . 19 10.3 aux and ddc ports . . . . . . . . . . . . . . . . . . . . 20 10.4 hpd input, hpd output. . . . . . . . . . . . . . . . . . 20 10.5 control inputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.6 status outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 12 soldering of smd packages . . . . . . . . . . . . . . 22 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 22 12.2 wave and reflow soldering . . . . . . . . . . . . . . . 22 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 12.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 26 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16 contact information . . . . . . . . . . . . . . . . . . . . 27 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: nxp: ? CBTL12131et,518

▲Up To Search▲

Price & Availability of CBTL12131

	To Download CBTL12131 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .